Compact hardware architecture for Hummingbird cryptographic algorithm

Abstract

Hummingbird is an ultra-lightweight cryptographic algorithm aiming at resource-constrained devices. In this paper, we present an enhanced hardware implementation of the Hummingbird cryptographic algorithm that is based on the memory blocks embedded within Spartan-3 FPGAs. The enhancement is not only from the introduction of the coprocessor approach but also from the employment of serialized data processing principles. Due to the compactness of the proposed architecture, remaining reconfigurable area in FPGAs can be used for other purposes. Comparisons to the other reported FPGA implementation of the Hummingbird cryptographic algorithm indicate that the proposed architecture outperforms the previous work in terms of both efficiency and area. We remark that our architecture can also be used as standalone although it is built via coprocessor approach