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dc.contributor.authorAt, Nuray
dc.contributor.authorBeuchat, Jean-Luc
dc.contributor.authorOkamoto, Eiji
dc.contributor.authorSan, İsmail
dc.contributor.authorYamazaki, Teppei
dc.date.accessioned2019-10-21T20:11:37Z
dc.date.available2019-10-21T20:11:37Z
dc.date.issued2014
dc.identifier.issn1549-8328
dc.identifier.issn1558-0806
dc.identifier.urihttps://dx.doi.org/10.1109/TCSI.2013.2278385
dc.identifier.urihttps://hdl.handle.net/11421/20273
dc.descriptionWOS: 000331191800015en_US
dc.description.abstractThe cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the algorithms considered in this work to deeply pipeline our Arithmetic and Logic Units, and to avoid data dependencies by interleaving independent tasks. We show for instance that a fully autonomous implementation of BLAKE and ChaCha on a Xilinx Virtex-6 device occupies 144 slices and three memory blocks, and achieves competitive throughputs. In order to offer the same features, a coprocessor implementing Skein and Threefish requires a substantial higher slice count.en_US
dc.description.sponsorshipJapanese Society of Promotion of Science (JSPS) through the A3 Foresight Program (Research on Next Generation Internet and Network Security)en_US
dc.description.sponsorshipThis work was supported in part by the Japanese Society of Promotion of Science (JSPS) through the A3 Foresight Program (Research on Next Generation Internet and Network Security). This paper was recommended by Associate Editor H.-C. Chang.en_US
dc.language.isoengen_US
dc.publisherIEEE-Inst Electrical Electronics Engineers Incen_US
dc.relation.isversionof10.1109/TCSI.2013.2278385en_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectCiphersen_US
dc.subjectCryptographyen_US
dc.subjectCoprocessorsen_US
dc.subjectField Programmable Gate Arraysen_US
dc.titleCompact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGAen_US
dc.typearticleen_US
dc.relation.journalIEEE Transactions On Circuits and Systems I-Regular Papersen_US
dc.contributor.departmentAnadolu Üniversitesi, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği Bölümüen_US
dc.identifier.volume61en_US
dc.identifier.issue2en_US
dc.identifier.startpage485en_US
dc.identifier.endpage498en_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.contributor.institutionauthorAt, Nuray


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