dc.contributor.author | At, Nuray | |
dc.contributor.author | Beuchat, Jean-Luc | |
dc.contributor.author | Okamoto, Eiji | |
dc.contributor.author | San, İsmail | |
dc.contributor.author | Yamazaki, Teppei | |
dc.date.accessioned | 2019-10-21T20:11:37Z | |
dc.date.available | 2019-10-21T20:11:37Z | |
dc.date.issued | 2014 | |
dc.identifier.issn | 1549-8328 | |
dc.identifier.issn | 1558-0806 | |
dc.identifier.uri | https://dx.doi.org/10.1109/TCSI.2013.2278385 | |
dc.identifier.uri | https://hdl.handle.net/11421/20273 | |
dc.description | WOS: 000331191800015 | en_US |
dc.description.abstract | The cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the algorithms considered in this work to deeply pipeline our Arithmetic and Logic Units, and to avoid data dependencies by interleaving independent tasks. We show for instance that a fully autonomous implementation of BLAKE and ChaCha on a Xilinx Virtex-6 device occupies 144 slices and three memory blocks, and achieves competitive throughputs. In order to offer the same features, a coprocessor implementing Skein and Threefish requires a substantial higher slice count. | en_US |
dc.description.sponsorship | Japanese Society of Promotion of Science (JSPS) through the A3 Foresight Program (Research on Next Generation Internet and Network Security) | en_US |
dc.description.sponsorship | This work was supported in part by the Japanese Society of Promotion of Science (JSPS) through the A3 Foresight Program (Research on Next Generation Internet and Network Security). This paper was recommended by Associate Editor H.-C. Chang. | en_US |
dc.language.iso | eng | en_US |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | en_US |
dc.relation.isversionof | 10.1109/TCSI.2013.2278385 | en_US |
dc.rights | info:eu-repo/semantics/openAccess | en_US |
dc.subject | Ciphers | en_US |
dc.subject | Cryptography | en_US |
dc.subject | Coprocessors | en_US |
dc.subject | Field Programmable Gate Arrays | en_US |
dc.title | Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA | en_US |
dc.type | article | en_US |
dc.relation.journal | IEEE Transactions On Circuits and Systems I-Regular Papers | en_US |
dc.contributor.department | Anadolu Üniversitesi, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği Bölümü | en_US |
dc.identifier.volume | 61 | en_US |
dc.identifier.issue | 2 | en_US |
dc.identifier.startpage | 485 | en_US |
dc.identifier.endpage | 498 | en_US |
dc.relation.publicationcategory | Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı | en_US |
dc.contributor.institutionauthor | At, Nuray | |